The present invention relates to a method of fabricating a MOSFET, and in particular a lightly doped drain MOSFET. More particularly, the present invention relates to a method of fabricating complementary self-aligned MOSFETs wherein a lightly doped drain n-channel device is complementarily arranged with either a zero drain overlap p-channel device or a lightly doped drain p-channel device.
It is widely known that conventional drain structure n-channel MOS devices can become unreliable at shorter channel lengths due to hot carrier effects. One way to overcome this problem is to modify the conventional drain structure such that the peak electric field at the drain edge is reduced. This can be achieved by reducing the drain doping density at the drain edge to produce a lightly doped drain (LDD) structure in the NMOS device. The LDD structure in the NMOS device may be formed by employing a sidewall spacer of silicon dioxide on the gate material.
In a typical known process to form n-channel LDD MOSFETs in a CMOS technology, n- and p-type wells are defined in silicon and are isolated by isolation oxide. The gate oxide is then formed and polysilicon gate electrodes are then patterned on the gate electrode oxide. The gate material and the sources and drains are then oxidized to grow 300-500 .ANG. of silicon dioxide. The p-type silicon layers are then masked off and p+ dopant is then implanted into the p-channel sources and drains. The mask is stripped off and then n-dopant is implanted into the entire device. A layer of silicon dioxide 2000-3000 .ANG. thick is deposited over the device and then the silicon dioxide is anisotropically etched back to form oxide sidewall spacers on the gate electrodes material. A layer of silicon dioxide up to 400 .ANG. thick is grown on the source/drain areas. The n-type silicon areas are masked off and n+dopant is implanted into the n-channel sources and drains. The device processing is completed through the formations of contacts and metallization. One difficulty in employing the known sidewall spacer technology in the manufacture of an LDD n-channel device in such a CMOS fabrication process is that the p-channel device must be masked during the LDD processing since the LDD implant penetrates all unmasked areas of the CMOS device being fabricated. Accordingly, an extra masking layer is required to protect areas of the CMOS device other than the n-channel device sources and drains.
An alternative process is described in "LDD MOSFETs Using Disposable Sidewall Spacer Technology" by James R. Pfiester, IEEE Electron Device Letters, Vol. 9, No. 4, April 1988. This paper discloses the fabrication of LDD MOSFET devices wherein the disposable sidewall spacers are provided on a thin polysilicon buffer layer which covers an oxidized polysilicon gate. The same masks can be used for both the light and heavy source/drain implants. However, the polysilicon buffer layer must be removed. Consequently, all of the sidewall spacers must also be removed. This is a serious disadvantage when the process is applied to devices which incorporate areas within the gate layer which are not intended to receive drain implants, such as SRAM cell loads as disclosed in, for example, U.S. Pat. No. A-4,471,374 and EP-A-0,197,871. If the polysilicon buffer layer is removed by thermal oxidation, this causes the growth of an oxide layer, typically 600 -700.ANG.thick, on the device which can block the source/drain implants.
EP-A-0218408 discloses a process for forming an LDD structure in integrated circuits which employs a two layer side wall spacer technology. The disclosed process is similar to that disclosed in the Pfiester article in that it employs a layer of LPCVD polysilicon to form side wall spacers, but this results in process limitations.
GB-A-2106315 discloses the manufacture of FETs in which sides of a polysilicon gate and line are oxidized. EP-A-0187260 discloses a MOSFET having an LDD-structure. EP-A-0111706 discloses a sidewall isolation for a gate of a field effect transistor. U.S. Pat. No. 4,729,002 discloses a semiconductor device provided with a MOSFET.
The present invention aims to overcome the above-mentioned problems of the prior art.